The proposed benchmarks were generated for the logic diagnosis of transition delay faults on gate level. The purpose of logic diagnosis is to find a pattern which will distinguish two faults, i.e. produce two different output responses for these faults. The transition delay fault model assumes that a defect will add an erroneous delay to a switching signal of at least one clock cycle. In the following we will briefly describe the structure of the benchmarks.

We used the standardized academic ISCAS'89 circuits (http://www.pld.ttu.ee/~maksim/benchmarks/iscas89/). Each benchmark instance will contain the encoding of two unrollings of a circuit which are required for the two time frames of a transition delay pattern. Furthermore it will contain the encoding of the output cones for a set of target faults which are supposed to be distinguished. Up to 200 target faults are possible. If two target faults are supposed to be distinguished from each other, additional logic is encoded which will determine whether the applied circuit inputs produce different output responses for the two faults. For each of these target fault pairs a soft clause is added, such that the number of distinguishable target fault pairs will be maximized. Furthermore, we have an additional requirement for detecting certain faults, which were determined in advance. For each of these faults we compute which logic signal values are required for their detection.

More details about diagnosis for transition delay faults and the construction of the corresponding MaxSAT instances can be found in [Riefert et al., Improving Diagnosis Resolution of a Fault Detection Test Set, VLSI Test Symposium, 2015].